1. Field of the Invention
The present invention relates to a method for determining an optimum initial value for efficient testing of an integrated circuit, including a large scale integrated circuit (VLSI), in a test pattern generator that generates a test pattern to be applied to the circuit under test.
2. Prior Art
With the increasing miniaturization of semiconductor processes, the costs of testing integrated circuits (including LSIs and VLSIs) have been increasing. If the operating speeds and integration levels of LSIs continue to increase at the present pace, more expensive testers than those used today would have to be used, over a long period of time, for LSI testing. To reduce test times on such expensive testers, extensive research has been conducted to find designs for easing the burden on testers by using design-for-testability techniques exemplified by scan design and built-in self-test (BIST) techniques.
BIST implements testing by integrating a test pattern generator (TPG) and a test response compactor (TRC) on the same chip as the circuit to be tested. This serves to ease the burden on the tester connected externally to the chip. A linear feedback shift register (LFSR) and a multiple input signature register (MISR) are often used as the TPG and the TRC, respectively.
A pseudo-random test pattern generator that uses an LFSR can apply a test pattern without using a tester, but has the shortcoming that, to achieve a high fault coverage exceeding 95%, a large number of test patterns become necessary and, as a result, the time required for testing, i.e., the test length, increases. Many attempts to overcome this shortcoming have been reported. One such attempt is a weighted pseudo-random sequence generating technique which assigns a weight to each bit in the test pattern to be applied to the circuit under test (hereinafter referred to as the CUT), and changes the probability of each bit being a 1 or a 0 in order to improve fault detection probability. (Refer, for example, to Literature 1 listed below.)
On the other hand, a method that inserts observation points and test points is intended to improve test quality by including the observation points and test points in the circuit under test and thereby improve the observability and controllability. However, as this method inserts observation points and test points in the CUT, the shortcoming is that the circuit structure of the CUT is changed and, hence, delay characteristics, etc. change. (Refer, for example, to Literature 2 listed below.)
With the above techniques alone, it is difficult to obtain sufficient fault coverage with limited test length. Therefore, BIST techniques that combine a random sequence with ATPG (Automatic Test-Pattern Generation) vectors are also being studied. (Refer, for example, to Literature 3, 4, and 5 listed below.)
There is also being studied a method that encodes a testcube as a seed for an LFSR by making use of the don't cares in the test code, and that performs testing by decoding the seed with the LFSR within the chip. In this reseeding method, each testcube is encoded by using an LFSR having a bit length equal to (the number of specified bits in the testcube+20) bits.
There is also a method called MP-LFSR which uses an LFSR having a plurality of feedback polynomials for testcube decoding. In this method, each testcube is encoded by using an MP-LFSR having a bit length equal to (the number of specified bits in the testcube+4) bits. (Refer, for example, to Literature 6 listed below.)
Bit-flipping BIST and bit-fixing BIST are each a method that finds a test pattern closest to the testcube from among the test patterns output from an LFSR, and applies the testcube by flipping or fixing some bits. These methods require a circuit for flipping or fixing bits.
According to the BIST techniques using the reseeding method, bit-flipping BIST, or bit-fixing BIST, first, easily detectable faults are detected using pseudo-random tests, and then reseeding of ATPG vectors is performed. These methods, first, perform pseudo-random tests using about 10,000 patterns. Then, ATPG vectors are applied to the remaining faults that have not been detected by the pseudo-random tests. To add the test vectors, the ATPG vectors must be applied from a tester or, in the case of BIST, a ROM, and if the number of undetected faults is large, the test cost increases.
To reduce the amount of hardware in the bit-flipping BIST or bit-fixing BIST circuitry, it is desirable to improve the quality of pseudo-random testing and thereby reduce the number of undetected faults. When the number of undetected faults is reduced, the tester storage capacity required can be reduced in the case of using a tester, and the internal ROM size can be reduced in the case of BIST.
One possible approach to improving the quality of pseudo-random testing is to improve the quality of pseudo-random testing by carefully selecting the seed. A method that makes use of a preobtained testcube is being studied. This method evaluates the test quality of the seed by the Hamming distance between the test pattern output from the LFSR and the testcube. By so doing, a seed of high test quality can be obtained with a reasonable amount of computation. (Refer, for example, to Literature 7 to 10 listed below.)
(Literature 1)
R. Kapur, S. Patil, T. J. Snethen, T, W. Williams, “Design of an Efficient Weighted Pattern Generation System,” Int'l Test Conf., pp. 491-500, 1994
(Literature 2)
H-C. Tsai, K-T. Cheng, S. Bhawmik, “Improving the Test Quality for Scan-based BIST Using a General Test Application Scheme,” DA Conf., pp. 748-753, 1999
(Literature 3)
G. Kiefer and H-J. Wunderlich, “Deterministic BIST with Scan Chains,” Int'l Test Conf., pp. 1057-1064,
(Literature 4)
G. Kiefer, H. Vranken, E. J. Marinissen, H-J. Wunderlich, “Application of Deterministic Logic BIST to Industrial Circuits,” Int'l Test Conf., pp. 105-114, 2000
(Literature 5)
D. Das, N. A. Touba, “Reducing Test Data Volume Using External/LBIST Hybrid Test Patterns,” Int'l Test Conf., pp. 115-122, 2000
(Literature 6)
S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, “Generation of Vector Patterns Through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers,” Int'l Test Conf., pp. 120-129, 1992
(Literature 7)
I. Bayraktaroglu, K. Udawatta, A. Oraologlu, “An Examination of PRPG Selection Approaches for Large Industrial Design,” Asia Test Symposium, pp. 440-444, 1998
(Literature 8)
I. Bayraktaroglu and A. Oraologlu, “Selecting a PRPG, Randomness, Primitiveness, or Sheer Luck?,” Asia Test Symposium, pp. 373-379, 2001
(Literature 9)
C. Fagot, O. Gascuel, P. Girard, C. Landrault, “A Ring Architecture Strategy for BIST Test Pattern Generation,” Asia Test Symposium, pp. 418-423, 1998
(Literature 10)
C. Fagot, O. Gascuel, P. Girard, C. Landrault, “On Calculating Efficient LFSR Seeds for Built-in Self Test,” Europe Test Conf., pp. 4-14, 1999
In the above integrated circuit testing methods using an LFSR, etc. as the test pattern generator, it is known that the test length required to achieve prescribed fault coverage differs if the initial value given to the test pattern generator differs. Accordingly, if the initial value that minimizes the test time can be selected in advance, the test time required in the mass production of integrated circuits can be reduced, and a drastic reduction in test cost can thus be achieved.
In the prior art, however, little attention has been paid to the initial value of the pattern generator, and a suitable value, such as 111 . . . 1 (all 1s), has simply been selected. As a result, if such an initial value, selected without paying any special consideration, is an inappropriate one, there is the possibility that the test length becomes enormously long.